1. Field of the Invention
The invention relates to a method for forming a semiconductor device, and more particularly, to a method for forming a semiconductor device with selective epitaxial growth (SEG) method.
2. Description of the Prior Art
As semiconductor processes advance to 65-nm node and beyond, and with the progress of device miniaturization, enhancing carrier mobility and a driving current of a Metal-Oxide-Semiconductor (MOS) transistor has become a critical issue. In order to improve a speed of the MOS transistor, a strained-silicon technique has been developed and is taken as a main solution to improve performance of the MOS transistor.
One approach of the strained-silicon technique is applied with selective epitaxial growth (SEG) method, which involves forming an epitaxial layer, such as a SiGe layer, on a single-crystalline silicon substrate while the crystalline orientation of the epitaxial layer is almost identical to that of the substrate. Because a lattice constant of the epitaxial SiGe layer is larger than that of silicon, such characteristic is employed to cause alteration to the band structure of the silicon in the channel region of the substrate. SEG method is widely applied in manufacturing numerous kinds of semiconductor devices, such as MOS transistors having raised source/drain regions which benefits from good short channel character and low parasitical resistance and MOS transistors having recessed source/drain which improves drain induced barrier lowering (DIBL) and punchthrough effect and reduces off-state current leakage and power consumption.
Please refer to FIGS. 1-2, which are schematic drawings illustrating a conventional method for manufacturing a MOS transistor utilizing SEG method. As shown in FIG. 1, a substrate 100 such as a silicon substrate is provided and a plurality of shallow trench isolation (STI) 102 is formed in the substrate 100. Then, a gate 110 is formed on the substrate 100 and followed by performing an ion implantation to form lightly doped drains (LDDs) 112 in the substrate 100 at two sides of the gate 110. Thus a channel region 114 is defined. Next, a spacer 116 is formed on sidewall of the gate 110 and recesses (not shown) are respectively formed in the substrate 100 at the two sides of the gate 110 by etching. Please still refer to FIG. 1. A SEG process is performed to form an epitaxial SiGe layer 120 along surfaces of the substrate 100 exposed in the bottom and sidewalls of the recess. And an ion implantation is performed before forming the recess or after the SEG process to form a recessed source/drain 118.
In principle, stress to the channel region 114 is increased as a Germanium (Ge) concentration in the epitaxial SiGe layer 120 is increased. Idealistically, the performance of the MOS transistor can be improved by increasing the Ge concentration. However, a thickness of the epitaxial SiGe layer 120 is limited by a critical thickness that is getting smaller when the Ge concentration is getting higher. If the thickness of the epitaxial SiGe layer 120 exceeds the critical thickness, it is relaxed and fails to cause stress to the channel region 114. Furthermore, when the Ge concentration in the epitaxial SiGe layer 120 is too high, a lattice mismatch between Si constituting the channel region 114 in the substrate 100 and SiGe becomes too high, thereby generating dislocation. As a result, stress provided by the epitaxial SiGe layer 120 is reduced, leakage current from the source/drain 188 is increased, and thus performance of the MOS transistor is deteriorated.
To avoid above-mentioned problem, the epitaxial SiGe layer 120 is formed with upward gradually-increasing Ge concentration by adjusting process factors during the SEG process. Or, as shown in FIG. 2, a multiple epitaxial SiGe layer 122, 124 is formed by performing different SEG processes with different process factors, while the epitaxial SiGe layer 124 possesses higher Ge concentration than the epitaxial SiGe layer 122. Those approaches are implied to improve stress to the channel region 114 under the critical thickness.
Please refer to FIG. 3, which is an enlarged schematic diagram of the epitaxial SiGe layer 120 in FIG. 2. It is well-known that the epitaxial layer 120 is formed along the surfaces of the substrate 100 at the bottom and sidewalls of the recess. The formation of the epitaxial SiGe layer 120 is proceeded as the upward growing epitaxial SiGe layer 120a, 120b, 120c, 120d, 120e shown in FIG. 3. Therefore, an islanding structure tightly adjacent to the spacer 116 is obtained as shown in FIG. 3. The islanding structure causes difficulties in following steps such as ion implantation or removing spacers, and eventually exerts influences upon the performance of the MOS transistor. It is noteworthy that due to the special growing characteristic found in the formation of the epitaxial layer, no matter if the epitaxial layer is formed as single epitaxial SiGe layer 120 having gradually-increasing Ge concentration which is obtained by adjusting process factors during one SEG process, or if the epitaxial layer is formed as a multiple epitaxial SiGe layer 122, 124 having different Ge concentration which is formed in different SEG process, said problem that the islanding structure tightly adjacent to the spacers 116 is always unavoidably found.